Synchronous and Asynchronous Multiplexer Circuits for Medical Imaging Realized in CMOS 0.18um Technology

Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. The purpose of these ASICs is to detect signals appearing randomly in many channels and to collect the detected data in an ordered fashion (de-randomization) in order to send it to an external ADC. ASIC output stage functionality can be divided into two: pulse detection and multiplexing. The pulse detection block is responsible for detecting maximum values of signals arriving from the shaper, sending a flag signal indicating that the peak signal has been detected and storing the pulse in an analog memory until read by ADC. The multiplexer in turn is responsible for searching for active flags, controlling the channel that has detected the peak signal and performing reset functions after readout. There are several types of multiplexers proposed in this paper, which can be divided into several classes: synchronous, synchronized and asynchronous. Synchronous circuits require availability of the multiphase clock generator, which increases the power dissipation, but simultaneously provide very convenient mechanism that enables unambiguous choice of the active channel. This characteristics leads to 100% effectiveness in data processing and no data loss. Asynchronous multiplexers do not require clock generators and because of that have simpler structure, are faster and more power efficient, especially when data samples occur seldom at the ASIC's inputs. The main problem of the asynchronous solution is when data on two or more inputs occur almost at the same time, shorter than the multiplexer's reaction time. In this situation some data can be lost. In many applications loss of the order of 1% of the data is acceptable, which makes use of asynchronous multiplexers possible. For applications when the lower loss is desirable a new hierarchy mechanism has been introduced. One of proposed solutions is a synchronized binary tree structure, that uses many simple asynchronous clock generators. This circuit joins advantages of synchronous and asynchronous solutions resulting in low power dissipation, high speed of operation and 100% effectiveness.

Published in:
Proceedings of the SPIE International Symposium on Microtechnologies for the New Millennium
Presented at:
SPIE International Symposium on Microtechnologies for the New Millennium, Gran Canaria, Spain, May 2-4, 2007

Note: The status of this file is: EPFL only

 Record created 2011-07-29, last modified 2018-12-03

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