Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography
2011
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Title
Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography
Author(s)
Sacchetto, Davide ; Xie, Shenqi ; Savu, Andreea Veronica ; Zervas, Michail ; De Micheli, Giovanni ; Brugger, Jürgen ; Leblebici, Yusuf
Published in
Proceedings of the 37th International Conference on Micro and Nano Engineering (MNE)
Conference
37th International Conference on Micro and Nano Engineering (MNE), Berlin, Germany, September 19-23, 2011
Date
2011
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LMIS1 - Microsystems Laboratory 1
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LSI1 - Integrated Systems Laboratory 1 (STI/IC)
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LMIS1 - Microsystems Laboratory 1
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date
2011-07-28