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Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography
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Vertically-Stacked Si Nanowire FETs with sub-micro[...]
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Sacchetto, Davide
et al
main
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MNE2011_2
version 1
MNE2011_2.pdf
[306.04 KB]
27 Jan 2018, 13:38
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