An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

Wireless Sensor Network (WSN) nodes require components with ultra-low power consumption, as they must operate without an external power supply. One technique for reducing consumption of a system is to scale it to a smaller technology; however, in recent technologies is not clear whether the decrease in dynamic power consumption outweighs the increase in static power consumption (due to leakage currents). Here this is considered by examining the power consumption of three implementations of an analog to digital converter (ADC). One in 350 nm, one in 180 nm, and one in 90 nm, were simulated and compared. The results show that the dynamic power consumption was reduced by a factor of four over the three technologies, but standby power consumption increased by an order of magnitude. The power consumption of the 180 nm implementation was always lower than the 350 nm implementation. However, assuming a WSN application with a duty cycle of 1%, the effective power consumption of the 90 nm ADC was higher than both the 180 nm and the 350 nm implementation. This highlights the dominance of leakage current in determining the effective power consumption in lowthroughput nodes.

Published in:
Proceedings of the Signal Processing Systems Design and Implementation, 2006. SIPS '06, 194-199
Presented at:
Signal Processing Systems Design and Implementation, 2006. SIPS '06, Banff, Canada, October 2-4, 2006

Note: The status of this file is: EPFL only

 Record created 2011-07-28, last modified 2018-03-17

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