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A conception as well as a CMOS implementation of the analog, ultra low power and fully parallel image processor have been presented in this paper. Proposed circuit bases on the 2-D FIR filters realized using the Gilbert vector multiplier. Proposed filter enables realization of various lowpass and highpass 2-D FIR filter masks. Both the mask dimensions and values of the filter coefficients can be programmed using several dozen digital signals and several DC currents. Proposed image processor does not use the clock generator, what simplifies the overall circuit's structure and reduces the noise level. An example (6times6) image processor that enables filtering with a 3times3 mask has been implemented in CMOS 0.18 mum process. This circuit calculates 36 pixels in parallel every 1 mus, dissipating power about 20 muW. The image resolution can be easily enlarged by a parallel connection of many designed 6times6 cells.