Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micrometer metal gate patterning for the first time. It is worth noting that the flexibility of this process enables the deposition of several gate materials, bypassing the conventional fabrication issues related to material etch selectivity. Finally, the excellent performance of individual FinFETs paves the way for the fabrication of more complex circuits.


Published in:
Proceedings of the 36th International Conference on Micro and Nano Engineering (MNE 2010)
Presented at:
36th International Conference on Micro and Nano Engineering (MNE 2010), Genova, Italy, September 19-22, 2010
Year:
2010
Keywords:
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 Record created 2011-07-26, last modified 2018-09-13

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