000167694 001__ 167694
000167694 005__ 20190316235155.0
000167694 037__ $$aCONF
000167694 245__ $$aAmbipolar silicon nanowire FETs with stenciled sub-µm metal gate
000167694 269__ $$a2010
000167694 260__ $$c2010
000167694 336__ $$aConference Papers
000167694 520__ $$aA fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micrometer metal gate patterning for the first time. It is worth noting that the flexibility of this process enables the deposition of several gate materials, bypassing the conventional fabrication issues related to material etch selectivity. Finally, the excellent performance of individual FinFETs paves the way for the fabrication of more complex circuits.
000167694 6531_ $$aSchottky barrier
000167694 6531_ $$aambipolarity
000167694 6531_ $$aSi nanowire
000167694 6531_ $$astencil lithography
000167694 6531_ $$aFET
000167694 6531_ $$asilicide
000167694 700__ $$0242417$$g181895$$aSacchetto, Davide
000167694 700__ $$0245968$$g176597$$aSavu, Veronica
000167694 700__ $$0240269$$g167918$$aDe Micheli, Giovanni
000167694 700__ $$aBrugger, Jürgen$$g145781$$0240120
000167694 700__ $$0240162$$g112194$$aLeblebici, Yusuf
000167694 7112_ $$dSeptember 19-22, 2010$$cGenova, Italy$$a36th International Conference on Micro and Nano Engineering (MNE 2010)
000167694 773__ $$tProceedings of the 36th International Conference on Micro and Nano Engineering (MNE 2010)
000167694 8564_ $$uhttps://infoscience.epfl.ch/record/167694/files/Sacchetto_MNE2010.pdf$$zn/a$$s288092$$yn/a
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000167694 909C0 $$xU10321$$0252040$$pLMIS1
000167694 909CO $$qGLOBAL_SET$$pconf$$pSTI$$pIC$$ooai:infoscience.tind.io:167694
000167694 917Z8 $$x112915
000167694 917Z8 $$x112915
000167694 917Z8 $$x112915
000167694 937__ $$aEPFL-CONF-167694
000167694 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000167694 980__ $$aCONF