Implementation of a 2 x 2 MIMO-OFDM receiver on an application specific processor

This paper describes the implementation of the hard computational kernels required for the baseband (BB) processing of a 2 x 2 multiple-input multiple-output (MIMO)-OFDM receiver on a design-framework for application specific processors. The employed low-complexity BB algorithms are described and their computational complexity is derived. The receiver is split into two parts which are mapped onto two application specific processors, each tailored to the computational needs of the associated digital signal processing kernels. The first processor performs the per stream MIMO-CFDM processing. The second processor handles the MIMO detection. Finally, the 0.18 mu m 1P/6M CMOS technology layout of both fabricated application specific processors is presented. Real-time BB processing is possible on these engines running at a clock frequency of 250 MHz. (C) 2009 Elsevier Ltd. All rights reserved.

Published in:
Microelectronics Journal, 40, 1642-1649
Presented at:
International Conference on Microelectronics, Cairo, EGYPT, Dec 29-31, 2007

 Record created 2011-06-06, last modified 2018-01-28

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