An IEEE 802.11a baseband receiver implementation on an application specific processor

This paper describes the implementation of the complete baseband processing of an IEEE 802.11a receiver on a design-framework for application specific processors. The underlying generic architecture is described, the computational kernels required for an IEEE 802.11a receiver are analyzed, and suitable processing units and architecture-configurations, to be defined at design-time, are identified. The discussion of the receiver implementation shows that the proposed architecture can meet real-time requirements on a 0.13 mu m CMOS process using a dock frequency of 160 MHz. The design demonstrates how the proposed standard-specific reconfigurable architecture is a valid alternative to ASIC and DSP implementations when looking for a balance between performance and flexibility.


Published in:
2007 50Th Midwest Symposium On Circuits And Systems, Vols 1-3, 1066-1069
Presented at:
50th Midwest Symposium on Circuits and Systems, Montreal, CANADA, Sep 05, 2007-Aug 08, 2008
Year:
2007
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
978-1-4244-1175-7
Keywords:
Laboratories:




 Record created 2011-06-06, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)