FPGA implementation of Viterbi decoders for MIMO-BICM

The FPGA implementation of Viterbi decoders for multiple-input multiple-output (MIMO) wireless communication systems with bit-interleaved coded modulation (BICM) and perantenna coding is considered. The paper describes how the recursive add-compare-select (ACS) unit, which constitutes the performance bottleneck of the circuit, can be pipelined to increase the throughput. As opposed to employing multiple parallel decoders, silicon area (resource utilization on the FPGA) is significantly reduced. The proposed optimizations lead to an implementation that achieves a throughput of 216 Mbps in a 4 x 4 MIMO-WLAN system prototype based on IEEE 802.11a.


Published in:
2005 39th Asilomar Conference on Signals, Systems and Computers, Vols 1 and 2, 734-738
Presented at:
39th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Oct 30-Nov 02, 2005
Year:
2005
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
1-4244-0131-3
Laboratories:




 Record created 2011-06-06, last modified 2018-01-28


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