Efficient ASIC implementation of a real-time depth mapping stereo vision system

This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo thatching and includes an occlusion detection method. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. A low-latency dataflow-oriented structure makes it possible to process 256 x 192 pixel Input streams with a rate In excess of 50 frames per second, amounting to more than 54 million pixel x disparity measurements per second (PDS) (for a 25-pixel disparity range), or roughly 18 GOPS. The design has been Integrated In a 0.25 mu m standard CMOS technology and occupies an area of less than 3 mm(2).

Published in:
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 1478-1481
Presented at:
46th IEEE International Midwest Symposium on Circuits and Systems, Cairo, EGYPT, Dec 27-30, 2003
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 Record created 2011-06-06, last modified 2018-09-13

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