VLSI implementation of MIMO detection using the sphere decoding algorithm

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the l(infinity)--instead of l(2)-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in [1]. The resulting ASICs currently rank among the fastest reported MIMO detector implementations.

Published in:
Ieee Journal Of Solid-State Circuits, 40, 1566-1577
Presented at:
30th European Solid-State Circuits Conference (ESSCIRC 2004), Leuven, BELGIUM, Sep 21-23, 2004

 Record created 2011-06-06, last modified 2018-03-17

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