VLSI implementation of MIMO detection using the sphere decoding algorithm
Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the l(infinity)--instead of l(2)-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.
Keywords: detection ; maximum likelihood (ML) ; multipleinput multiple-output (MIMO) ; spatial multiplexing ; sphere decoding ; very large scale integration (VLSI) ; wireless communications ; Lattice ; Complexity ; Search ; Point
Record created on 2011-06-06, modified on 2016-08-09