Variable delay ripple carry adder with carry chain interrupt detection

A statistical approach for the area efficient implementation of fast wide operand adders using early termination detection is described and analyzed. It is shown that high throughput can be achieved based on area- and routing-efficient ripple-carry adders with only marginal overhead. They share a low AT-product with Brent-Kung adders but provide designers with totally different area/delay tradeoffs. The circuit does not require full-custom design and fits well into both self-timed and synchronous designs.


Published in:
Proceedings Of The 2003 Ieee International Symposium On Circuits And Systems, Vol V, 113-116
Presented at:
IEEE International Symposium on Circuits and Systems, BANGKOK, THAILAND, May 25-28, 2003
Year:
2003
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
0-7803-7761-3
Laboratories:




 Record created 2011-06-06, last modified 2018-03-17


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)