An ASIC implementation of adaptive arithmetic coding

In this work, we present an improved version of an ASIC implementation of the adaptive arithmetic coding algorithm which uses a two-level memory hierarchy. We propose algorithmic modifications and a special hardware structure to speed-up the design without degrading the compression ratio obtained using this memory hierarchy. Moreover, several new features which increase the compression efficiency are introduced. Finally, a VLSI implementation based on the results of our work is presented.


Published in:
Thirty-Sixth Asilomar Conference On Signals, Systems & Computers - Conference Record, Vols 1 And 2, Conference Record, 1078-1083
Presented at:
36th Asilomar Conference on Signals, Systems and Computers, PACIFIC GROVE, CA, Nov 03-06, 2002
Year:
2002
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
0-7803-7576-9
Laboratories:




 Record created 2011-06-06, last modified 2018-03-17


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