Analysis of power consumption on switch fabrics in network routers

In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.


Published in:
Proceedings of the 39th annual Design Automation Conference (DAC)
Presented at:
39th annual Design Automation Conference (DAC), New Orleans, Louisiana, USA, June 10-14, 2002
Year:
2002
ISBN:
1-58113-461-4
Laboratories:




 Record created 2011-05-05, last modified 2018-03-17

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