This paper presents the state-of-the-art of nanostencil as a direct and local patterning method. Stencil lithography is a high-resolution shadow mask technique that allows structuring surfaces without using the harsh process steps typically associated with photolithography (solvents, high temperature baking, etc.). Our work has concentrated on studying the technique and maximizing its potential in terms of resolution, scalability to full wafer, and applicability to various material systems. We found solutions to align the stencils to 100 mm substrates and reach sub-100 nm patterning capabilities by reducing the gap to the substrate and circumventing the aperture clogging during material deposition [1, 2]. We also used stencil lithography as an enabling technique for cost-efficient patterning of unconventional substrates. Thus, recently we have applied stencil lithography to a variety of new MEMS/NEMS, where other lithography methods would fail or would be prohibitively expensive. We patterned superconducting tunnel junctions[3], metallic nanowires [4, 5] and nanodots for plasmonic applications [6] on planar rigid substrates. On flexible substrates we micro-fabricated organic electronics, using up to 3 aligned stencil lithography steps [7]. Metallic catalysts were nanopatterned through stencil on semi-released cantilevers. This allowed for a high throughput fabrication of C nanotubes and Si nanowire scanning probes [8]. The stencil can be used in a dynamic mode, by moving in situ relative to the substrate while material is evaporated [9]. This allows for custom “design” of patterns using standard apertures in the stencil, including thickness-variable structures and closed-loop geometries not available otherwise with a static stencil. This paper provides an overview of the current capabilities of nanostencil lithography, showing some of the most recent scientific highlights and concrete application examples.