A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions


Published in:
Proceedings of the Workshop on Cryptographic Hardware Embedded Systems (CHES)
Presented at:
Workshop on Cryptographic Hardware Embedded Systems (CHES), Lausanne, Switzerland, September 6-9, 2009
Year:
2009
Laboratories:




 Record created 2011-04-07, last modified 2018-03-18


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)