This paper describes some of the design experiences achieved during the design, simulation and characterization of a Complementary Metal-Oxide Semiconductor (CMOS) LNA which has been designed for 24GHz and fabricated in a standard 0.180 µm technology. More specifically, some technological limitations of the CMOS process for mm-wave applications are considered, before showing the outcomes of the schematic and post-layout simulations as well as the measurements and discussing the reasons for the difference between simulations and measurements. It is shown that the simulation results can be significantly improved using Electro-Magnetic (EM) post-layout simulations. Moreover, a post-layout simulation methodology allowing a straightforward integration of the EM simulations into the workflow is proposed.