This paper presents a modeling methodology for substrate current coupling mechanisms. An enhanced model of the diode ensuring continuity of minority carriers is used to build an equivalent schematic, accounting for minority and majority carrier propagation in the substrate. For the first time a typical H-bridge structure is simulated with the proposed methodology. The parasitic current injected in the substrate by a high-voltage structure is simulated in a circuit-level simulator as well as with a finite elements method. Both are compared to measurements and show a very good agreement. The simulation resources needed by the proposed equivalent schematics are thus greatly reduced in regard to the finite element approach, offering an efficient tool for substrate modeling in smart power IC's.