Integrated Hall devices have the great advantage, over other magnetic sensors, that they can be fully fabricated by a standard CMOS process. However they are known to have a relatively large offset (i.e. residual voltage at zero magnetic field). Techniques such as spinning current [1] or orthogonal coupling are effective to reduce this offset down to the 100 uT range. Still, in order to gain a real advantage over competing technologies [2], the offset of integrated Hall sensors should be reduced further, to the 10 uT range. The idea to achieve low offset performances is to reduce the sensor non-linearities. According to the reverse field reciprocity principle [3], the spinning current method completely cancels the offset in a linear system. It is now well understood that the major cause of non-linearity is either the junction field effect [4] or the carrier velocity saturation, depending on the device geometry. In both cases the non-linearity increases with the device bias voltage. However, reducing the bias voltage to reduce offset degrades the signal to noise ratio, since the noise depends mainly on device resistance. Therefore, the solution to maintain the signal-to-noise ratio is to integrate an array of Hall devices. This architecture allows finding a good trade-off between offset reduction, sensitivity, bandwidth, and current consumption. We have realized a system in 0.35 um CMOS standard technology to demonstrate the potential of this architecture. A primitive cell containing a Hall device, spinning current block and an amplification unit was designed in order to build an arbitrarily large array. This particular test system is built of 16 primitive cells, equally distributed over the layout. The Hall signal is processed in a differential way and can be demodulated using time continuous or switched capacitor technique, depending on required signal bandwidth. In addition, a switching scheme designed to reduce the problems of charge injection and the related switching spikes was implemented. Promising results are shown and the relation between parameters, such as the bias current, the number of cells, the layout distribution and the selected signal treatment technique, are discussed.