Variable latency speculative addition: A new paradigm for arithmetic circuit design

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, and circuits with performance close to these bounds have been designed. In this paper we present a novel adder design that is exponentially faster than traditional adders; however it produces incorrect results, deterministically, for a very small fraction of input combinations. We have also constructed a reliable version of this adder that can detect and correct mistakes when they occur. This creates the possibility of a variable-latency adder that produces a correct result very fast with extremely high probability; however in some rare cases when an error is detected, the correction term must be applied and the correct result is produced after some time. Since errors occur with extremely low probability, this new type of adder is significantly faster than state-of-the-art adders when the overall latency is averaged over many additions.

Published in:
2008 Design, Automation And Test In Europe, Vols 1-3, 1092-1097
Presented at:
Design, Automation and Test in Europe Conference and Exhibition (DATE 08), Munich, GERMANY, Mar 10-14, 2008
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

 Record created 2010-11-30, last modified 2018-03-17

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