CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications

The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies oil the charge-based processing of sum-of-products terms, complemented with digital post-processing. The synthesis of complex functions such as winner-(loser)-take-all, k-winner-(loser)-take-all, rank ordering are demonstrated with a minimal hardware overhead. Different operation modes and corresponding hardware configurations are presented. The VLSI realization of the core two-dimensional Hamming distance discriminator, and the chip measurements are discussed. As such, the presented Hamming discriminator is uniquely suitable for real-time image processing and alignment applications. (C) 2008 Elsevier Ltd. All rights reserved.

Published in:
Microelectronics Journal, 39, 1817-1828

 Record created 2010-11-30, last modified 2018-03-17

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