A Low-Noise CMOS Receiver Frontend for MRI
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V power supply, it has a measured input referred noise density of only 0.6 nV/root Hz. The receiver consists of a reception coil, an on-chip tuning capacitor, a low-noise amplifier, and a 50 Omega output buffer. The system is designed for operation in a B-0-field of 7 Gamma corresponding to a frequency of 300MHz. It is implemented in a 0.35 mu m CMOS high-voltage process and occupies a chip area of 850 mu m x 500 mu m.
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Record created on 2010-11-30, modified on 2016-08-09