A Novel FPGA Logic Block for Improved Arithmetic Performance

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 x compared to adder trees synthesized using ternary adders.

Published in:
Fpga 2008: Sixteenth Acm/Sigda International Symposium On Field-Programmable Gate Arrays, 171-180
Presented at:
16th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb 24-26, 2008
Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa

 Record created 2010-11-30, last modified 2018-01-28

Rate this document:

Rate this document:
(Not yet reviewed)