In this paper design options when implementing programmable sampling rate converters are discussed. The theory and performance of the classical and new converters based on maximum order and minimum support (MOMS) splines is presented. FPGA designs are shown in term of resources used, latency, and the quality of results. Second-order (or, equivalently, linear or triangular) and sine-based benchmarks are described and evaluated that show the advantages of the new MOMS-based sampling rate converters. The FPGA synthesis results of 7 different converters are presented as proof of concept.