An Integrated CMOS Receiver Chip for NMR-Applications

We present the first CMOS-only receiver chip for NMR-applications at 300 MHz. The system consists of an on-chip reception coil, a tuning-capacitor, a downconversion-mixer and a low-frequency gain-stage as well as biasing and offset-compensation circuitry. It has an input referred voltage noise density of 0.7 nV/root Hz and a gain of 75dB. The power consumption is 18 mA from a single 3.3 V supply. The chip is realized in 0.35 mu m technology and occupies an area of 1200 x 850 mu m(2).


Published in:
Proceedings Of The Ieee 2009 Custom Integrated Circuits Conference, 471-474
Presented at:
IEEE Custom Integrated Circuits Conference, San Jose, CA, Sep 13-16, 2009
Year:
2009
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
Laboratories:




 Record created 2010-11-30, last modified 2018-03-17


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