Using 3D Integration Technology To Realize Multi-Context Fpgas

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). The latency between reconfigurations, 8.42 mu s, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.


Published in:
Proceedings of the International Conference on Field Programmable Logic and Applications, 507-510
Presented at:
International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, Aug 31-Sep 02, 2009
Year:
2009
Publisher:
IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA
Keywords:
Laboratories:




 Record created 2010-11-30, last modified 2018-09-13


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