A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up the convergence of the message passing decoding algorithm. To avoid routing congestion the decoder architecture employs a novel communication scheme that reduces the critical number of global wires by 50%. The prototype LDPC decoder ASIC, fabricated in 90 nm CMOS, occupies only 5.35 mm^2 and achieves a decoding throughput of 11.69 Gb/s at 1.2 V with an energy efficiency of 133 pJ/bit.

Published in:
Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC)
Presented at:
IEEE Asian Solid-State Circuits Conference (A-SSCC), Bejiing, China, November 8-10

 Record created 2010-11-22, last modified 2018-03-18

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