Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 um.


Published in:
Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System
Presented at:
18th IEEE/IFIP International Conference on VLSI and System-on-Chip , Madrid, Spain, September 27-29
Year:
2010
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
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 Record created 2010-11-17, last modified 2018-09-13

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