3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI supports stacking active layers such that fine-grain integration of 3-D circuits can be implemented. This paper extends the idea of constructing the standard cells across two active layers, forming 3-D cells, to reduce the overall area and interconnect wirelength of a circuit. To demonstrate the effect of the 3DMI technology on these important parameters of circuit design, two important communication blocks are evaluated. Specifically, a low-density-parity-check (LDPC) decoder as a sample of interconnect-dominated circuit and a data-encryption-standard (DES) block, which is good instance of a gate dominated circuit, are investigated. By employing 3-D cells in the conventional design flow chain, there is more than 10% decrease in wirelength for both circuits (in wirelength driven placement mode). However, when subjected to timing driven placement a slight reduction in delay (1.6%) is observed for an LDPC decoder, whereas for the DES block considerable delay reduction (14.22%) is achieved.