Asymmetrically strained all-silicon Tunnel FETs featuring 1V operation

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/I off characteristics. We demonstrate that a lateral strain profile with a maximum of strain higher than 3GPa at the BTB source junction could act as an effective performance Tunnel FET enabling the cancelation of the drain threshold voltage. We study and report in detail the contributions of main technology boosters of all-silicon Tunnel FETs: (i) strained source, (ii) high-k gate dielectric, (iii) multiple-gate, (iv) oxide alignment to i-region and (v) channel length scaling, as an additive device optimization enabling future sub-IV operation. ©2009 IEEE.

Published in:
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, null, null, 452-455

 Record created 2010-11-08, last modified 2018-01-28

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