In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon Tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire Tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: 1) ultralow I-off (more than three decades lower than in the case of a device on uniformly strained silicon); 2) boosting of I-on (more than one decade higher compared to a silicon reference); and 3) an average subthreshold swing S-avg of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the Tunnel FET, which could be a disadvantage for logic design with Tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side.