Smart Power IC simulation of substrate coupled current due to majority and minority carriers transports

This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.


Publié dans:
2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, 168-171
Année
2010
Laboratoires:




 Notice créée le 2010-11-04, modifiée le 2019-08-12


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