000154138 001__ 154138
000154138 005__ 20190812205440.0
000154138 0247_ $$2doi$$a10.1109/ICICDT.2010.5510261
000154138 037__ $$aCONF
000154138 245__ $$aSmart Power IC simulation of substrate coupled current due to majority and minority carriers transports
000154138 269__ $$a2010
000154138 260__ $$c2010
000154138 336__ $$aConference Papers
000154138 520__ $$aThis paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.
000154138 700__ $$0242732$$g147260$$aLo Conte, F.
000154138 700__ $$0241224$$g106334$$aSallese, Jean-Michel
000154138 700__ $$aKayal, M.$$0240539$$g105540
000154138 773__ $$t2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010$$q168-171
000154138 909C0 $$xU11978$$pELAB$$0252315
000154138 909C0 $$pEDLAB$$0252605
000154138 909CO $$pconf$$pSTI$$ooai:infoscience.tind.io:154138
000154138 917Z8 $$x102085
000154138 917Z8 $$x144315
000154138 937__ $$aEPFL-CONF-154138
000154138 973__ $$rNON-REVIEWED$$sPUBLISHED$$aEPFL
000154138 980__ $$aCONF