000153570 001__ 153570
000153570 005__ 20190812205438.0
000153570 020__ $$a83-922632-4-3
000153570 0247_ $$2doi$$a10.1109/MIXDES.2007.4286127
000153570 037__ $$aCONF
000153570 245__ $$aStructured design based on the inversion factor parameter: Case study of ΔΣ modulator system
000153570 269__ $$a2007
000153570 260__ $$c2007
000153570 336__ $$aConference Papers
000153570 500__ $$aEPFL, Electronics Labs., STI/IMM/LEG, CH-1015 Lausanne, Switzerland Marvell Switzerland Sarl, Route de Pallatex 17, CH-1163 Etoy, Switzerland, Export Date: 19 January 2010, Source: Scopus, Art. No.: 4286127, References: Enz, C., Krummenacher, F., Vittoz, E., An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications (1995) Analog Integrated Circuits and Signal Processing, pp. 83-114. , Kluwer Academic Publishers; Kayal, M., Randjelovic, Z., Auto-zero differential difference amplifier (2000) Electronics Letters, 36, pp. 695-696; Stefanovic, D., Krummenacher, F., Pastre, M., Kayal, M., BSIM2EKV: Un outil pour la conversion automatique des paramèters du modèle BSIM aux paramèteres du modèle EKV (2004) TAISA'04 5ème colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, pp. 85-88; Bult, K., Geelen, G., A fast-settling CMOS op amp for SC circuits with 90-dB DC gain (1990) IEEE Journal of Solid-State Circuits, 25, pp. 1379-1384; Stefanovic, D., Kayal, M., Pastre, M., Litovski, V., Procedural analog design (PAD) tool (2003) Fourth International Symposium on Quality Electronic Design, pp. 313-318; Stefanovic, D., Kayal, M., Pastre, M., PAD: A New Interactive Knowledge-Based Analog Design Approach (2005) Analog Integrated Circuits and Signal Processing Journal, 42, pp. 291-299
000153570 520__ $$aThis paper presents the design flow from system-level specifications to transistor-level design for three different fully-differential amplifiers composing the first and the second integrator of a second-order hybrid multi-bit ΔΣ modulator. The circuit-level specifications for each amplifier are extracted using behavioral models and timedomain system-level simulations with a SNDR target value of 93 dB ± 2 dB. The amplifiers are designed using the structured analog design methodology consisting of circuit partitioning into basic analog blocks, specification derivation for each basic block, and transistor sizing in a specific design sequence. Transistor-level design is based on the choice of the inversion factor and the transistor length to achieve the required specifications of each block. After all three analog amplifiers are sized, the system-level performance is confirmed by time-domain simulations, and the obtained SNDR value is within the specified range. Copyright © 2007 by Department of Microelectronics & Computer Science, Technical University of Lodz.
000153570 6531_ $$aΔΣ modulator
000153570 6531_ $$aFolded cascode OTA
000153570 6531_ $$aFully-differential amplifier topology
000153570 6531_ $$agm/I d methodology
000153570 6531_ $$aInversion factor
000153570 6531_ $$aStructured analog design
000153570 6531_ $$aTransistor-level design
000153570 700__ $$aStefanovic, D.
000153570 700__ $$aPesenti, S.
000153570 700__ $$0244585$$g111342$$aPastre, M.
000153570 700__ $$aKayal, M.$$g105540$$0240539
000153570 7112_ $$dJune 21-23, 2007$$cCiechocinek, Poland$$aMixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on
000153570 773__ $$tProceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07.$$q95-102
000153570 8564_ $$zURL$$uhttp://tinyurl.com/2uuxcql
000153570 909C0 $$xU11978$$pELAB$$0252315
000153570 909CO $$ooai:infoscience.tind.io:153570$$qGLOBAL_SET$$pconf$$pSTI
000153570 917Z8 $$x198375
000153570 937__ $$aEPFL-CONF-153570
000153570 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000153570 980__ $$aCONF