CMOS Current Steering Logic: Toward a matured technique for mixed-mode applications
Saez, R. T. L.; Kayal, M.; Declercq, M.
1997

Abstract

This paper presents a detailed analysis of the CMOS Current Steering Logic (CSL) technique and compares experimentally its digital switching noise to that of the CMOS static logic. Theoretical analysis of the CSL inverter is developed. More complex gates using this technique are presented. Results are validated by simulations and measurement.

Details

Title CMOS Current Steering Logic: Toward a matured technique for mixed-mode applications
Author(s) Saez, R. T. L. ; Kayal, M. ; Declercq, M.
Published in Proceedings of the Ieee 1997 Custom Integrated Circuits Conference
Pages 349-352
Conference IEEE 1997 Custom Integrated Circuits Conference, Santa Clara, CA, May 05-08, 1997
Date 1997
DOI https://doi.org/10.1109/CICC.1997.606645
Other identifier(s) View record in Web of Science
Laboratories ELAB
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > ELAB - Electronics Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2010-10-21

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