CMOS Current Steering Logic: Toward a matured technique for mixed-mode applications

This paper presents a detailed analysis of the CMOS Current Steering Logic (CSL) technique and compares experimentally its digital switching noise to that of the CMOS static logic. Theoretical analysis of the CSL inverter is developed. More complex gates using this technique are presented. Results are validated by simulations and measurement.


Published in:
Proceedings of the Ieee 1997 Custom Integrated Circuits Conference, 349-352
Year:
1997
Note:
Times Cited: 2
IEEE 1997 Custom Integrated Circuits Conference
May 05-08, 1997
Santa clara, ca
Laboratories:




 Record created 2010-10-21, last modified 2018-03-17


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