A 1.3V low-power 430 MHz front-end using a standard digital CMOS process

A low-power and low-voltage (LP/LV) RF front-end operating at 430MHz and implemented in a standard 0.5 mu m digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 mu A LNA, two different 50 mu A mixers and a ring-oscillator with differential I-Q outputs consuming 300 mu A at 430MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17dB was achieved, together with a spurious free dynamic range of 55dB at 60kHz bandwidth, which is sufficient for the targeted application.


Published in:
Ieee 1998 Custom Integrated Circuits Conference - Proceedings, 503-506
Year:
1998
Note:
Times Cited: 5
IEEE Custom Integrated Circuits Conference
May 11-14, 1998
Santa clara, ca
Laboratories:




 Record created 2010-10-21, last modified 2018-01-28


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