Journal article

Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates

This paper presents a modeling strategy to simulate the propagation of electrical perturbations induced by direct biasing of substrate junctions. Usually, this is done by identifying parasitic substrate devices such as bipolar transistors. However, mapping a topology with these bipolar transistors rapidly reaches its limits when several junctions are acting at the same time. In this paper, we propose a new modeling methodology of parasitic signals. It relies on a generalized model of p-n junctions and resistances that takes into account minority-carrier densities and gradients at the boundaries. We show that bipolar-transistor- and thyristor-related effects can be obtained from a network interconnection of these extended devices. Furthermore, we show that this modeling approach could be easily extended to simulate complex 3-D layouts. © 2009 IEEE.

    Keywords: Integrated circuit (IC) ; Lumped modeling ; Methodology modeling ; Noise ; Parasitic coupling ; Power parasitic modeling ; Power semiconductor devices ; Smart Power IC ; Substrate modeling


    Ecole Polytechnique Fédérale de Lausanne, 1015 Laussane, Switzerland

    Export Date: 19 January 2010

    Source: Scopus

    Art. No.: 5339188

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    Record created on 2010-10-21, modified on 2017-06-01


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