000153539 001__ 153539
000153539 005__ 20190812205438.0
000153539 02470 $$2ISI$$a000262463700036
000153539 037__ $$aCONF
000153539 245__ $$aSubstrate current modeling for high-voltage smart power BCD technology
000153539 269__ $$a2008
000153539 260__ $$c2008
000153539 336__ $$aConference Papers
000153539 500__ $$aLaboratoire d'Electronique Générale (LEG), Ecole Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Cited By (since 1996): 2, Export Date: 19 January 2010, Source: Scopus, Art. No.: 4606341, References: Murari, B., Bertotti, F., Vignola, G.A., (2002) Smart power ICs: Technologies and applications, , 2nd Edition, Springer, Berlin; Clement, F.J.R., Zysman, E., Kayal, M., Declercq, M., LAYIN: Toward a global solution for parasitic coupling modeling and visualization (1994) Custom Integrated Circuits Conference, pp. 537-540; Mitra, S., Rutenbar, R.A., Carley, L.R., Allstot, D.J., A methodology for rapid estimation of substrate-coupled switching noise (1995) Custom Integrated Circuits Conference, pp. 129-132; Schenkel, M., Pfàffli, P., Mettler, S., Reiner, W., Wilkening, W., Aemmer, D., Fichtner, W., Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection (2000) Solid-State Device Research Conference, pp. 600-603; Kayal, M., Saez, R.L., Pastre, M., The Reduction of switching noise using CMOS current steering logic (2003) Substrate Noise Coupling in Mixed-Signal ASICs, pp. 223-228. , Kluwer
000153539 520__ $$aThis paper presents a compact- and a macro-model for estimating and simulating the perturbations induced in the substrate by high-voltage transistors switching inductive loads. On one hand, it allows the designer to predict the amount of switching noise generated by a particular topology. On the other hand, it enables a wise choice of the positioning of sensitive low-voltage circuits around the noisy devices, as well as the choice of appropriate shielding structures. The models proposed are validated by measurements on a prototype circuit at 25°C. © 2008 IEEE.
000153539 6531_ $$aIntegrated circuit modeling
000153539 6531_ $$aNoise coupling
000153539 6531_ $$aPower parasitic modeling
000153539 6531_ $$aPower semiconductor devices
000153539 6531_ $$aSubstrate modeling
000153539 700__ $$0242732$$g147260$$aLo Conte, F.
000153539 700__ $$0244585$$g111342$$aPastre, M.
000153539 700__ $$aSaliese, J. M.
000153539 700__ $$g105583$$aKrummenacher, F.$$0241225
000153539 700__ $$aKayal, M.$$g105540$$0240539
000153539 7112_ $$dJune 22-25, 2008$$cMontreal, QC, Canada$$aCircuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
000153539 773__ $$tProceedings of the Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008$$q141-144
000153539 8564_ $$zURL$$uhttp://tinyurl.com/28mbxyd
000153539 909C0 $$xU11978$$pELAB$$0252315
000153539 909CO $$ooai:infoscience.tind.io:153539$$qGLOBAL_SET$$pconf$$pSTI
000153539 917Z8 $$x198375
000153539 937__ $$aEPFL-CONF-153539
000153539 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000153539 980__ $$aCONF