Gate-lag and drain-lag effects in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs

Gate and drain-lag effects are studied in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs grown on sapphire. Electron trapping on the surface states between the gate and the drain forming the net negative charge up-to similar to 2 x 10(13) cm(-2) is found to be responsible for the gate-lag effect in the (GaN)/InAlN/GaN HEMTs. If the polarization charge at the device surface is decreased by GaN capping, then density of the trapped charge is not changed, however the electron de-trapping process becomes faster. The drain-lag effect is caused by electron injection and trapping in the source-gate area reaching similar to 1 x 10(13) cm(-2) of the trapped charge in the steady state. In the studied voltage range the InAlN/AlN/GaN HEMT is shown to be gate-lag-free suggesting that this parasitic transient can be avoided if thin AlN is used in the epi-layer growth sequence. It is assumed that this breakthrough quality relates to the decreased or even reverted electric field in the MAIN layer if AlN is inserted. Surface states need not to be generated in this case. (c) 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Published in:
Physica Status Solidi a-Applications and Materials Science, 204, 6, 2019-2022

 Record created 2010-10-05, last modified 2018-03-17

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