000150473 001__ 150473
000150473 005__ 20190717172520.0
000150473 0247_ $$2doi$$a10.5075/epfl-thesis-4832
000150473 02470 $$2urn$$aurn:nbn:ch:bel-epfl-thesis4832-3
000150473 02471 $$2nebis$$a6126909
000150473 037__ $$aTHESIS
000150473 041__ $$aeng
000150473 088__ $$a4832
000150473 245__ $$aArchitecture of a Real-Time Platform Independant GPS L1 Software Receiver
000150473 269__ $$a2010
000150473 260__ $$bEPFL$$c2010$$aLausanne
000150473 300__ $$a196
000150473 336__ $$aTheses
000150473 520__ $$aPersonal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable mobile devices is driving the interest of software receiver solutions as they provide several advantages with respect to traditional hardware implementations. First, they share the same system resources such as the processor, embedded memory and power with other system units, reducing both the size and the costs of their integration. Second, they can be easily reprogrammed – via a firmware update – for incorporating the latest developments, such as the exploitation of the future satellites signals or some improved multipath mitigation techniques. Finally, they offer a more flexible solution for rapid research and development as compared to conventional hardware receivers where the chip design is fixed and obtained after a long integration process. With the increasing performance of modern processors, it becomes now feasible to implement in software a multi-channel GPS receiver operating in real-time. However, a major problem with the software architecture is the large computing resources required for the digital signal processing. Former studies have demonstrated that a straightforward transposition of traditional hardware based architectures into software would lead to an amount of integer operations which is not suitable for today's fastest computers. From this observation, several strategies have been proposed in the literature in order to reduce the complexity of the receiver operations. The first one relies on the utilization of advanced microprocessor instructions set which provides the capability of processing vectors of data by operating on multiple integer values at the same time. This results in significant gains in execution speed, but also severely limits the portability of the code, since the operations are tied to specific processors architectures. Another alternative consists in exploiting the native bitwise representation of the signal. The data bits are stored in separate vectors on which logical parallel operations can be performed. The objective is to take advantage of the universality, high parallelism, and speed of the bitwise operations for which a single integer operation translates into a few simple parallel logical relations. However, the inherent drawback of the bitwise processing is the lack of flexibility as the complexity becomes bit-depth dependent. This thesis has been carried out in the framework of a two-year industrial project (2007-2009) in collaboration with U-blox AG in Thalwil. It aimed to the realization of a multi-channel, platform-independent real-time GPS L1 software receiver. The main challenge of this project consisted in providing real-time performances while keeping the portability of the code to make the receiver suitable for any type of software implementation. In that sense, new techniques and algorithms have been developed for optimizing the processing chain in order to lower the processor load. The main idea consists in regrouping data which share the same characteristics, and process them in batches instead of sequentially. This way, it becomes possible to progressively reduce the data throughput and consequently the amount of operations to perform. A completely new receiver architecture has been proposed and validated through the realization of a functional prototype, thus demonstrating the feasibility of the concept.
000150473 6531_ $$aGPS
000150473 6531_ $$asoftware receiver
000150473 6531_ $$areal-time
000150473 6531_ $$abatch processing
000150473 6531_ $$aplatform-independent
000150473 6531_ $$anew architecture
000150473 6531_ $$acomputational load
000150473 6531_ $$aGPS
000150473 6531_ $$arécepteur logiciel
000150473 6531_ $$atemps réel
000150473 6531_ $$atraitement par lot
000150473 6531_ $$aportabilité
000150473 6531_ $$anouvelle architecture
000150473 6531_ $$acharge de calcul
000150473 700__ $$aWaelchli, Grégoire
000150473 720_2 $$aFarine, Pierre-André$$edir.$$g152066$$0243688
000150473 720_2 $$aBotteron, Cyril$$edir.$$g190010$$0243672
000150473 8564_ $$zTexte intégral / Full text$$yTexte intégral / Full text$$uhttps://infoscience.epfl.ch/record/150473/files/EPFL_TH4832.pdf$$s5260109
000150473 909C0 $$xU11964$$pESPLAB$$0252263
000150473 909CO $$pthesis$$pthesis-bn2018$$pthesis-public$$pDOI$$ooai:infoscience.tind.io:150473$$qDOI2$$qGLOBAL_SET$$pSTI
000150473 918__ $$bSTI-SMT$$cIMT$$aSTI
000150473 919__ $$aESPLAB
000150473 920__ $$b2010
000150473 970__ $$a4832/THESES
000150473 973__ $$sPUBLISHED$$aEPFL
000150473 980__ $$aTHESIS