Conference paper

Experimental Kohonen Neural Network Implemented in CMOS 0.18μm Technology

In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been realized using building blocks proposed earlier by the authors, such as binary tree current-mode winner takes all (WTA) circuit, Euclidean distance calculation circuit (EDC), adaptive weight change mechanism (AWC), conscience mechanism (CONS), initial weight initialization mechanism (IB). The network performance has been verified in the way of measurements. The obtained measurement results are in a good agreement with theoretical considerations as well as HSPICE simulations. The circuit occupies a chip area (without pads) equal to 0.07 mm2 and consumes 1 mW of power for 1.8 V supply. The input currents are in the range between 1 and 7 μA. We intend to apply the designed KNN to analyze ECG biomedical signals.


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