Current-mode Memory Cell with Power Down Phase for Discrete Time Analog Iterative Decoders

A low power, current-mode memory element for analog discrete time iterative decoders is proposed. In the circuit a high-speed power-down mechanism has been implemented that enables a significant increase of the operation speed without increasing the power dissipation. During the power down phase the data stored in the memory is maintained in the capacitor. The proposed memory element works at a sampling frequency of 10 MSps. During the normal operation the memory cell dissipates power of 1.5-?W, while in the standby phase 50-nW.

Published in:
proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)
Presented at:
International Symposium on Circuits and Systems (ISCAS), Seatle, USA,, May 18-21, 2008.

Note: The status of this file is: EPFL only

 Record created 2010-08-17, last modified 2018-01-28

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