Asymmetrically strained all-silicon multi-gate n-Tunnel FETs
This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW.
Keywords: Tunnel FET ; Band-to-band tunneling ; Local lateral uniaxial tensile strain ; Asymmetric strain profile ; Local strain engineering ; Local band-gap modulation ; Subthreshold swing ; CMOS downscaling ; Multi-gate ; Si nanowire ; FP7
Record created on 2010-08-10, modified on 2016-08-08