Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW.


Published in:
Solid State Electronics, 54, 9, 935-941
Year:
2010
Publisher:
Elsevier
ISSN:
0038-1101
Keywords:
Laboratories:




 Record created 2010-08-10, last modified 2018-03-17

Fulltext:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)