Integration of Engineered Source and Drain Extensions in Double Gate Mosfet with Sub-32nm Channel Length
Since the advent of CMOS technology, the semiconductor industry has been successful in achieving continuously improved performance. The feature size of the most important electronic device, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), has already be reduced from about 10 µm to sub 100 nm regime during the last 30 years. The enormous miniaturization and integration of MOSFET devices has made possible a dramatic development in microelectronics. However, many challenges exit and have to be addressed to achieve sub-30 nm devices: increased Source/Drain (S/D) resistances, excessive gate oxide leakage and deteriorated device performance due to short channel effects (SCE). In order to keep Moore's Law living, device scaling down is not any more enough. To keep pace with scaling several technological booster have been introduced such as SiGe or Metallic material for S/D, high-k dielectric as a gate material, SOI or strained silicon for channel material and multi gate architecture. Double Gate (DG) architecture is believed to be used for beyond 22 nm node because of its advantage in terms of preserving the electrostatic integrity. The key issue introduced by DG is misalignment which can be overcome by fabricating self aligned structure. However this device suffers from the series resistance. Hence S/D can be engineered either by introducing new material like SiGe or Ge (Band gap engineering) or silicidation induced Dopant Segregation (DS). In both case, current can be improved by enhanced carrier injection from source to channel and reducing series resistance. This thesis includes the method to integrate the S/D in DG structure. We start with identifying the conditions (implantation and annealing) to achieve high active dopants in thin film S/D and SiGe integrated S/D. In additions to this, means to implant the extension in scaled devices are explored. In the second step, the processes and conditions are developed for etching, epitaxy and silicidation. It is demonstrated that contact resistivity down to 0.1 Ω.µm2 can be obtained by integrating PtSi S/D suitable for p-MOSFETs. The final DG devices after integrating S/D are characterized and analyzed. The electric potential of the architecture DG in terms of control of SCE and mobility are exploited. The transport mechanism (Thermionic or Tunneling) is understood by performing the static device measurement at low (77 °K) to high (363 °K) temperatures. Schottky barrier heights of as low as 0.1eV and access resistance of 250 Ω.µm are demonstrated with our proposed and fabricated devices, thanks to DS metallic S/D. These results can be considered as being at the level of the state of the art for metallic S/D device today.
Keywords: CMOS ; Double Gate ; Etching ; Epitaxy ; Silicidation ; Dopant Segregation ; Series resistance ; CMOS ; Double-Grille ; Epitaxie ; Gravure ; Siliciuration ; Ségrégation de dopants ; Résistance sériesThèse École polytechnique fédérale de Lausanne EPFL, n° 4824 (2011)
Programme doctoral Microsystèmes et Microélectronique
Faculté des sciences et techniques de l'ingénieur
Institut de génie électrique et électronique
Laboratoire des dispositifs nanoélectroniques
Record created on 2010-08-05, modified on 2016-08-08