000150054 001__ 150054
000150054 005__ 20190416220651.0
000150054 0247_ $$2doi$$a10.1109/TCAD.2010.2061610
000150054 022__ $$a0028-0070
000150054 02470 $$2ISI$$a000284417400012
000150054 037__ $$aARTICLE
000150054 245__ $$aSunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips
000150054 269__ $$a2010
000150054 260__ $$c2010
000150054 336__ $$aJournal Articles
000150054 520__ $$aThree-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3-D and 2-D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3-D NoC when compared to the corresponding 2-D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.
000150054 6531_ $$a3-D integrated circuits (3D-ICs)
000150054 6531_ $$anetworks on chip (NoC)
000150054 6531_ $$aplacement
000150054 6531_ $$asynthesis
000150054 6531_ $$atopology
000150054 6531_ $$aOn-Chip
000150054 6531_ $$aInterconnection Networks
000150054 6531_ $$aDesign
000150054 6531_ $$aGeneration
000150054 6531_ $$aArchitectures
000150054 6531_ $$aPerformance
000150054 700__ $$0242416$$g172199$$aSeiculescu, Ciprian
000150054 700__ $$0242414$$g171633$$aMurali, Srinivasan
000150054 700__ $$g171049$$aBenini, Luca$$0243773
000150054 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000150054 773__ $$j29$$tIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems$$k12$$q1987-2000
000150054 8564_ $$uhttps://infoscience.epfl.ch/record/150054/files/TCAD2010_seiculescu-1.pdf$$zn/a$$s1752902$$yn/a
000150054 909C0 $$xU11140$$0252283$$pLSI1
000150054 909CO $$particle$$ooai:infoscience.tind.io:150054$$qGLOBAL_SET$$pSTI$$pIC
000150054 917Z8 $$x176271
000150054 917Z8 $$x176271
000150054 917Z8 $$x139598
000150054 937__ $$aEPFL-ARTICLE-150054
000150054 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000150054 980__ $$aARTICLE