000150051 001__ 150051 000150051 005__ 20190316234827.0 000150051 020__ $$a978-1-4503-0037-7 000150051 0247_ $$2doi$$a10.1145/1811100.1811107 000150051 037__ $$aCONF 000150051 245__ $$aProcess-induced skew variation for scaled 2-D and 3-D ICs 000150051 269__ $$a2010 000150051 260__ $$bACM Press$$c2010$$aNew York, New York, USA 000150051 336__ $$aConference Papers 000150051 520__ $$aTechnology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented at scaled technology nodes and for a 3-D circuit with an increasing number of planes is investigated in this paper. An accurate model used to describe the effect of the proper sources of variations on each of these design approaches is proposed. The distribution of the pair-wise skew variation is obtained for single scaled or multi-plane (not scaled) clock distribution networks. The accuracy of the presented statistical skew model is verified through Monte-Carlo simulations. As shown in this paper, the clock skew variation due to technology scaling and/or die stacking exhibits a considerably different behavior. A comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency. A popular global clock tree topology is employed in a planar (2-D) circuit where technology scaling is applied and in a 3-D circuit with an increasing number of planes. For this clock tree topology, the maximum supported clock frequency increases from 2.75 GHz to 3.74 GHz by proper die-stacking at a 90 nm technology node. 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling. 000150051 6531_ $$a3-d ics 000150051 6531_ $$aclock distribution networks 000150051 6531_ $$aclock skew 000150051 6531_ $$aprocess variations 000150051 6531_ $$atechnology scaling 000150051 700__ $$0242420$$g183772$$aXu, Hu 000150051 700__ $$aPavlidis, Vasilis F. 000150051 700__ $$aDe Micheli, Giovanni$$g167918$$0240269 000150051 7112_ $$dJune 13, 2010$$cAnaheim, California, USA$$a12th ACM/IEEE International Workshop on System Level Interconnect Prediction - SLIP '10 000150051 773__ $$tProceedings of the 12th ACM/IEEE International workshop on System level interconnect prediction - SLIP '10$$q17-24 000150051 8564_ $$uhttps://infoscience.epfl.ch/record/150051/files/p17-xu.pdf$$zn/a$$s1173731$$yn/a 000150051 909C0 $$xU11140$$0252283$$pLSI1 000150051 909CO $$pIC$$qGLOBAL_SET$$ooai:infoscience.tind.io:150051$$pconf$$pSTI 000150051 917Z8 $$x128933 000150051 917Z8 $$x176271 000150051 917Z8 $$x112915 000150051 937__ $$aEPFL-CONF-150051 000150051 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL 000150051 980__ $$aCONF