Scalable Instruction Set Simulator for Thousand-core Architectures Running on GPGPUs
2010
Files
Details
Title
Scalable Instruction Set Simulator for Thousand-core Architectures Running on GPGPUs
Author(s)
Raghav, Shivani ; Ruggiero, Martino ; Atienza, David ; Pinto, Christian ; Marongiu, Andrea ; Benini, Luca
Published in
Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS 2010)
Pages
459-466
Conference
Workshop on Exploitation of Hardware Accelerators (WEHA 2010), Caen, France, June 28- July 2, 2010
Date
2010
Publisher
New Jersey, USA, IEEE Press
ISBN
978-1-4244-6828-7
Laboratories
ESL
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > ESL - Embedded Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date
2010-07-12