An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Architecture and Receiver

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-μm digital CMOS process with 0.6-V threshold voltage. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s.

Published in:
IEEE Journal of Solid-State Circuits, 36, 3, 452-466
Other identifiers:
Scopus: 2-s2.0-0035275044

 Record created 2010-06-24, last modified 2018-01-28

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